As soon as a significant deviation in interference emission or in interference immunity of EMC tests is detected, question arises not only about a possible solution, but always about actual cause. In many development departments, the trail-and-error method is then used to find a quick solution. The actual physical cause usually remains hidden.
If a finished design, which has been optimised according to the trail-and-error method, is later developed into further product variants, the old deviations in EMC performance reappear in a large number of cases. Further “optimisations” are hardly or no longer possible here according to the named method. The developer finds himself in the situation of having to decide on a completely new development, and this in the advanced design phase. The only remedy for the situation described above is to make a conscious decision to search for the physical cause when an EMC problem is first detected. If the physical cause is known, correct approach to solving the problem is almost automatic. Instead of investing time in trail-and-error it is better used in root-cause analysis.
Analysis takes place not only, but usually, at PCB level. Many – from an EMC point of view often very different – components and assemblies are installed here and can interact with each other. The primary goal of root cause analysis is to find interaction and to name a corrective measure. Let’s take as an example a signal input of the device under development, which was examined for interference during the EMC test. The interference comes from the device and couples out to the environment (e.g. connected periphery) via signal line. Signal integrity suffers from this interference on the one hand, and on the other hand EMC test is not passed.
Practising root cause analysis means to look for the source of the fault. This can be, for example, a switch-mode power supply (SMPS). However, the source is not cause alone, because according to the circuit diagram disturbances from power supply cannot reach to signal line at all (e.g. filters are present, or a spatial distance between SMPS and signal line connection is given on the PCB). Another cause is a coupling on PCB between source (SMPS) and sink (signal line connection), which is not yet known. Finding this coupling is a core task in this analysis method. Coupling types can be e.g. magnetic or electrical coupling, displacement currents, ground bouncing, low damping between adjacent conductors, to name some physical causes.
At the end of the analysis, not only source and sink can be clearly named, but also the coupling path between them and the physical reason for coupling. In best case, this results in 3 possible solutions: Optimisation at source, at coupling path and at sink. These solutions can be tested easily and quickly (e.g. during the test in the EMC laboratory). However, in practice it often turns out that more preparation must be invested in coupling path; ideally, it no longer exists after optimisation!